The present invention relates generally to demodulating binary information and, more particularly to demodulation of frequency shift keying (FSK) transmissions.
Frequency shift keying (FSK) is a frequency modulation scheme whereby digital information can be transmitted by discrete changes of a carrier wave frequency. A simple form of FSK is the so-called binary frequency shift keying (BFSK) where a logical “1” is represented by a first frequency (F1, say) of a carrier wave and a logical “0” is represented by a second frequency (F2) of the carrier wave. One known method for de-modulating binary FSK signals uses a comparator to resolve the incoming modulated waveform into a square wave by comparing the received signal amplitude with a threshold. A counter/timer circuit monitors the frequency of state transactions of the square waves in order to determine a count of transitions per time period. In an alternative method, the counter/timer circuit measures an amount of time taken to complete a pre-defined number of transitions. A decision device selects a frequency from a predetermined set of frequencies which most closely corresponds to the measurement, and decodes a bit value ‘0’ or ‘1’ corresponding to the selected frequency. This solution works satisfactorily when there is an appreciable difference between the frequencies F1 and F2 so that a typical counter/timer clock frequency running at around 40 MHz would be sufficient for resolving them. However, for FSK frequencies which are much closer together, such as that defined by the Wireless Power Consortium WPC-QI standard where a difference of 31.25 ns is specified, employing the conventional circuitry described above would require a counter/timer clock running at around 128 MHz. This is very difficult to implement with current microcontroller technology. A modulation scheme specified by the ‘Wireless Power Consortium WPC-QI standard specifies that for a given number of cycles (e.g., 512 cycle) of the received FSK signal comprising one bit, if the carrier wave stays at a constant frequency (F1 or F2), a logical “0” is represented in such period; otherwise if the carrier wave switches its frequency (e.g., from F1 to F2 or F2 to F1 in the middle of this given period), then a logical “1” is represented in this period.
Thus it would be advantageous to provide a counter/timer-based FSK demodulator that can operate with a system clock frequency that is readily achievable with existing microcontroller technology and that is compatible with the Wireless Power Consortium standard and protocol.